View MC74VHC02DR2_750056.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC74VHC02 Quad 2-Input NOR Gate
The MC74VHC02 is an advanced high speed CMOS 2-input NOR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
http://onsemi.com MARKING DIAGRAMS
14 SOIC-14 D SUFFIX CASE 751A 1 VHC02G AWLYWW
* * * * * * * * * * * *
High Speed: tPD = 3.6 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 40 FETs or 10 Equivalent Gates Pb-Free Packages are Available*
1
14 TSSOP-14 DT SUFFIX CASE 948G 1 1 VHC 02 ALYW G G
A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
A1 B1 A2 B2 A3 B3 A4 B4
2 3 5 6 8 9 11 12
1
PIN ASSIGNMENT
Y1 Y1 A1 Y2 Y=A+B B1 Y2 A2 B2 GND Y4 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC Y4 B4 A4 Y3 B3 A3
4
10
Y3
13
Figure 1. LOGIC DIAGRAM
FUNCTION TABLE
Inputs A L L H H B L H L H Output Y H L L L
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
1
November, 2005 - Rev. 4
Publication Order Number: MC74VHC02/D
MC74VHC02
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I II I I I I I I II I I I I I I I II I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I III II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIII IIIIIIIIIIIIIIIIIII I III II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I II I I IIIII I I I II II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I IIII I I II I IIIIIIIIII II I I I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIII IIIIIIIII I III II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I II I IIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I III II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIII III I III II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIII IIIIIII IIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIII I I I I IIIIIII I I I I III II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I III I I III I I II I I I III I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I I III I I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III III I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I
II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III II I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I III IIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol VCC Vin IIK Vout IOK Iout PD ICC Parameter Value Unit V V V DC Supply Voltage DC Input Voltage - 0.5 to + 7.0 - 0.5 to + 7.0 DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 50 500 450 Input Diode Current mA mA mA mA Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW _C Tstg - 65 to + 150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin TA Vout tr, tf Parameter Min 2.0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage
DC Output Voltage
VCC 100 20
Operating Temperature
- 40 0 0
+ 85
_C
Input Rise and Fall Time
VCC = 3.3V 0.3V VCC =5.0V 0.5V
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH Parameter
Test Conditions
VCC V
TA = 25C Typ
TA = - 40 to 85C Min Max
Min
Max
Unit V
Minimum High-Level Input Voltage
2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5
1.50 VCC x 0.7
1.50 VCC x 0.7
VIL
Maximum Low-Level Input Voltage
0.50 VCC x 0.3
0.50 VCC x 0.3
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL IOH = - 50mA
1.9 2.9 4.4
2.0 3.0 4.5
1.9 2.9 4.4
V
Vin = VIH or VIL IOH = - 4mA IOH = - 8mA Vin = VIH or VIL IOL = 50mA
2.58 3.94
2.48 3.80
VOL
Maximum Low-Level Output Voltage
0.0 0.0 0.0
0.1 0.1 0.1
0.1 0.1 0.1
V
Vin = VIH or VIL IOL = 4mA IOL = 8mA Vin = 5.5 V or GND Vin = VCC or GND
0.36 0.36
0.44 0.44
Iin
Maximum Input Leakage Current
0 to 5.5 5.5
0.1 2.0
1.0 20.0
mA mA
ICC
Maximum Quiescent Supply Current
http://onsemi.com
2
MC74VHC02
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I I I I IIIIIIIIIIIIIIIIIIIIII I II III IIIIIIIIIIII I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II III I III I III I IIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I II III I II III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL Parameter TA = 25C Typ 5.6 8.1 3.6 5.1 4 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 Max 9.5 13.0 6.5 8.5 10 Test Conditions Min Max 7.9 11.4 5.5 7.5 10 Unit ns Maximum Propagation Delay, Input A or B to Output Y VCC = 3.3 0.3V VCC = 5.0 0.5V CL = 15pF CL = 50pF CL = 15pF CL = 50pF Cin Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0V
15 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Characteristic Typ 0.3 - 0.3 Max 0.8 - 0.8 3.5 1.5 Unit V V V V
TEST POINT A or B 50% tPLH Y 50% VCC *Includes all probe and jig capacitance tPHL VCC GND DEVICE UNDER TEST OUTPUT C L*
Figure 2. Switching Waveforms
Figure 3. Test Circuit
INPUT
Figure 4. Input Equivalent Circuit
ORDERING INFORMATION
Device MC74VHC02DR2 MC74VHC02DR2G MC74VHC02DTR2 MC74VHC02DTR2G Package SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* Shipping 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
http://onsemi.com
3
MC74VHC02
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
http://onsemi.com
4
EEE CCC EEE CCC
MC74VHC02
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
5
MC74VHC02/D

▲Up To Search▲

Price & Availability of MC74VHC02DR2

	To Download MC74VHC02DR2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .